View NCV7718DPR2G_7970468.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2012 september, 2012 ? rev. 0 1 publication order number: ncv7718/d ncv7718 hex half-bridge driver the ncv7718 is a hex half ? bridge driver with protection features designed specifically for automotive and industrial motion control applications. the ncv7718 has independent controls and diagnostics. the device can be operated in forward, reverse, brake, and high impedance states. the drivers are controlled via a 16 bit spi interface and are daisy chain compatible. features ? low quiescent current sleep mode ? high ? side and low ? side drivers connected in a half ? bridge configuration ? integrated freewheeling protection (ls and hs) ? 0.55 a peak current ? r ds(on) = 1 (typ) ? 5 mhz spi control ? compliance with 5 v and 3. 3 v systems ? undervoltage and overvoltage lockout ? discriminated fault reporting ? overcurrent protection ? overtemperature protection ? under load detection ? daisy chain compatible with multiple of 8 bit devices ? 16 ? bit frame detection ? these are pb ? free devices typical applications ? automotive ? industrial ? dc motor management for hvac application marking diagram http://onsemi.com ncv7718g awlyyww ncv7718 = specific device code a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package ssop24 nb case 506al see detailed ordering and shipping information in the package dimensions section on page 26 of this data sheet. ordering information
ncv7718 http://onsemi.com 2 shown below is a typical application for the ncv7718 configuration. voltage regulator uc watchdog ncv7718 out2 so si sclk csb vcc high side switch high side switch high side switch high side switch high side switch high side switch low side switch low side switch low side switch low side switch low side switch low side switch out3 out4 out5 out6 out1 protection: under load over temperature under ? voltage over ? voltage over current vs2 16 ? bit serial data interface power on reset logic control gnd en mra4003t3 13.2v vs1 gnd gnd gnd figure 1. typical application
ncv7718 http://onsemi.com 3 enable bias por spi 16 bit logic and latch fault reporting en vcc so si sclk csb vs1 drive2 control logic wave shaping wave shaping low side driver high side driver fault ls under load overcurrent drive1 out1 vs vs out2 vs2 vs over voltage lockout vs1 & vs2 vref1 under voltage lockout vref2 gnd drive3 vs out3 drive4 vs out4 drive5 vs out5 drive6 vs out6 gnd gnd vref1 thermal warning & shutdown vs vref2 gnd vs1 & vs2 figure 2. block diagram
ncv7718 http://onsemi.com 4 gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 20 22 23 24 figure 3. pinout ? ssop24 out1 out5 nc vcc so en nc out6 out4 gnd si out2 nc vs1 sclk csb reserved reserved vs2 nc out3 gnd package description the pin ? out for the hex half ? bridge in ssop24 package is shown in the table below. pin # ssop24 symbol description 1 gnd ground. shorted to pin 24 internally. 2 out1 half bridge output 1 3 out5 half bridge output 5 4 nc no connection. this pin should be isolated from any traces or via on the pcb board. 5 si serial input. 16 bit serial communications input. 3.3 v/5 v (ttl) compatible. internally pulled down. 6 vcc power supply input for logic. 7 so serial output. 16 bit serial communications output. 3.3 v/5 v complaint 8 en enable. input high wakes the ic up from a sleep mode. 3.3 v/5 v (ttl) compatible. internally pulled down. 9 nc no connection. this pin should be isolated from any traces or via on the pcb board. 10 out6 half bridge output 6 11 out4 half bridge output 4 12 gnd ground. shorted to pin 13 internally. 13 gnd ground. shorted to pin 12 internally. 14 out3 half bridge output 3 15 nc no connection. this pin should be isolated from any traces or via on the pcb board. 16 vs2 voltage power supply input for the drivers 3, 4 and 6. this pin must be connected to vs1 externally. 17 reserved reserved for internal use. this pin must be grounded. 18 reserved reserved for internal use. this pin must be grounded. 19 csb chip select bar. active low serial port operation. 3.3v/5v (ttl) compatible. internally pulled up. 20 sclk serial clock. clock input for use with spi communication. 3.3 v/5 v (ttl) compatible. internally pulled down. 21 vs1 voltage power supply input for the drivers 1, 2 and 5, all the pre ? drivers and the charge pump. this pin must be connected to vs2 externally. 22 nc no connection. this pin should be isolated from any traces or via on the pcb board. 23 out2 half bridge output 2 24 gnd ground. shorted to pin 1 internally.
ncv7718 http://onsemi.com 5 maximum ratings rating symbol value unit power supply voltage (vs1, vs2) (dc) (ac), t < 500ms, ivsx > ? 2a vsxdcmax vsxac ? 0.3 to 40 ? 1.0 v output pin outx (dc) (ac) (ac), t< 500ms, ioutx > ? 1.1a (ac), t< 500ms, ioutx < 1a voutxdc voutxac ? 0.3 to 40 ? 0.3 to 40 ? 1.0 1.0 v pin voltage (logic input pins, si, sclk, csb, so, en, vcc) viomax ? 0.3 to 5.5 v output current (out1, out2, out3, out4, out5, out6) ioutximax ? 2.0 to 2.0 a electrostatic discharge, human body model, vsx, outx vesd4k 4.0 kv electrostatic discharge, human body model, all other pins vesd2k 2.0 kv electrostatic discharge, machine model vesd200 200 v short circuit reliability characterization aecq10x grade a ? operating junction temperature tj ? 40 to 150 c storage temperature range tstr ? 55 to 150 c moisture sensitivity level (max 260 c processing) msl3 3 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. thermal information (note 1) rating symbol value unit junction to ambient r ja 95.2 c/w junction to lead r jl 62 c/w 1. thermal information is based on having 3 high side and 3 low side devices dissipating 80 mw each on a 2 layer board 0.062 thick fr4 board with 600 mm 2 copper spreader area. 2 oz copper is used for the copper spreader area and the ambient temperature is specified at 25 c. recommended operating conditions rating symbol value unit min max digital supply input voltage vccop 3.15 5.25 v battery supply input voltage vsxop 5.5 28 v dc output current ixop ? 0.55 a junction temperature tjop ? 40 125 c
ncv7718 http://onsemi.com 6 electrical characteristics ( ? 40 c < t j < 150 c, 5.5 v < vsx < 40 v, 3.15 v < v cc < 5.25 v, en = v cc , unless otherwise specified) characteristic symbol conditions min typ max unit general supply current (vs1 + vs2) sleep mode iqvsx85 vs1 = vs2 = 13.2 v, v cc = 0 v ? 40 c to 85 c ? 1.0 2.5 a supply current (vs1 + vs2) active mode ivsop en = v cc , 5.5 v < v sx < 28 v no load ? 2.5 5.0 ma supply current (v cc ) sleep mode active mode iqv cc iv cc op csb = v cc , en = si = sclk = 0 v ( ? 40 c to 85 c) en = csb = v cc , si = sclk = 0 v no load ? ? 1.0 1.5 2.5 3.0 a ma total sleep mode current i(vs1) + i(vs2) + i(vcc) iqtot sleep mode, ? 40 c to 85 c ? 2 5 a v cc power ? on ? reset threshold vccpor v cc increasing ? 2.55 2.9 v vsx undervoltage detection threshold vsxuv v sx decreasing 3.7 4.1 4.5 v vsx undervoltage detection hysteresis vsxuhys 100 ? 450 mv vsx overvoltage detection threshold vsxov v sx increasing 32 36 40 v vsx overvoltage detection hysteresis vsxohys 1 2.5 4 v thermal response thermal warning twr not ate tested 120 140 170 c thermal warning hysteresis twhy not ate tested ? 20 ? c thermal shutdown ts d not ate tested 150 175 200 c thermal shutdown hysteresis tsdhy not ate tested ? 20 ? c outputs output high r ds(on) (source) rdsonhs i out = ? 500 ma 6 v < v s < 40 v ? 1 2.25 output low r ds(on) (sink) rdsonls i out = 500 ma 6 v < vs < 40 v ? 1 2.25 source leakage current isrclkg13.2 isrclkg40 out(1 ? 6) = 0 v, v sx = 13.2 v, v cc = 5 v out(1 ? 6) =0 v, v sx = 40 v, v cc = 5 v ? 1.0 ? 5.0 ? ? ? ? a sink leakage current isnklkg13.2 isnklkg40 out(1 ? 6) = v sx = 13.2 v, v cc = 5 v out(1 ? 6) = v sx = 40 v, v cc = 5 v ? ? ? ? 1.0 5.0 a overcurrent shutdown threshold (source) isdsrc v cc = 5 v, v sx = 13.2 v ? 2.0 ? 1.2 ? 0.8 a overcurrent shutdown threshold (sink) isdsnk v cc = 5 v, v sx = 13.2 v 0.8 1.2 2.0 a over current delay timer tdoc 10 25 50 s under load detection threshold (low side) iuldls v cc = 5 v, v sx = 13.2 v 2.0 11 20 ma under load detection delay time tduld v cc = 5 v, v sx = 13.2 v 200 350 600 s body diode power transistor body diode forward voltage vbdfwd if = 500 ma ? 0.9 1.3 v
ncv7718 http://onsemi.com 7 electrical characteristics ( ? 40 c < t j < 150 c, 5.5 v < vsx < 40 v, 3.15 v < v cc < 5.25 v, en = v cc , unless otherwise specified) characteristic unit max typ min conditions symbol logic inputs (en, si, sclk, csb) input threshold high low vthinh vthinl 2.0 ? ? ? ? 0.6 v input hysteresis (si, sclk, csb) vthinhys 50 150 300 mv enable hysteresis vthenhys 150 400 800 mv input pull ? down resistance (en, si, sclk) rpdx en = si = sclk = v cc 50 125 200 k input pull ? up resistance (csb) rpucsb csb = 0 v 50 125 250 k input capacitance cinx not ate tested ? ?? 15 pf logic output (so) output high vsoh i source = ? 1 ma v cc ? 0.6 ? ? v output low vsol i sink = 1.6 ma ? ? 0.4 v tri ? state leakage itristlkg csb = 5 v ? 5 ? 5 a tri ? state input capacitance itristcin csb = v cc , 0 v < v cc < 5.25 v not ate tested ? ? 15 pf
ncv7718 http://onsemi.com 8 electrical characteristics ( ? 40 c < tj < 150 c, 5.5 v < vsx < 40 v, 3.15 < vcc < 5.25 v, en= vcc, unless otherwise specified) characteristic symbol conditions timing chart min typ max unit driver output timing specifications high side turn on time thson vs = 13.2 v, r load = 70 ? 7.5 13 s high side turn off time thsoff vs = 13.2 v, r load = 70 ? 3.0 6.0 s low side turn on time tlson vs = 13.2 v, r load = 70 ? 6.5 13 s low side turn off time tlsoff vs = 13.2 v, r load = 70 ? 2.0 5.0 s high side rise time thstr vs =13.2 v, r load = 70 ? 4.0 8.0 s high side fall time thstf vs = 13.2 v, r load = 70 ? 2.0 4.0 s low side rise time tlstr vs = 13.2 v, r load = 70 ? 1.0 3.0 s low side fall time tlstf vs = 13.2 v, r load = 70 ? 1.0 3.0 s high side off to low side on non ? overlap time thsofflson vs = 13.2 v, r load = 70 1.5 ? ? s low side off to high side on non ? overlap time tlsoffhson vs = 13.2 v, r load = 70 1.5 ? ? s serial peripheral interface sclk frequency fclk ? ? 5.0 mhz sclk clock period tpclk v cc = 5 v v cc = 3.3 v 200 500 ? ? ? ? ns sclk high time tclkh 1 85 ? ? ns sclk low time tclkl 2 85 ? ? ns sclk setup time tclksup 3 4 85 85 ? ? ? ? ns si setup time tsisup 11 50 ? ? ns si hold time tsih 12 50 ? ? ns csb setup time tcsbsup 5 6 100 100 ? ? ? ? ns csb high time (note 2) tcsbh 7 5.0 ? ? s so enable after csb falling edge tenso 8 ? ? 200 ns so disable after csb rising edge tdisso 9 ? ? 200 ns so rise time tsor c load = 40 pf not ate tested ? ? 10 25 ns so fall time tsof c load = 40 pf not ate tested ? ? 10 25 ns so valid time tsov c load = 40 pf sclk to so 50%, not ate tested 10 ? 20 50 ns en low valid time tenl v cc = 5 v en going low 50% to outx turing off 50% 10 ? ? s en high to spi valid tenhspiv ? ? 100 s srr delay between two consecutive frame (note 3) tsrr 150 ? ? s 2. this is the minimum time the user must wait between spi commands 3. this is the minimum time the user must wait to send a srr command between consecutive frames. if tsrr time is not met the srr request is ignored.
ncv7718 http://onsemi.com 9 electrical characteristic timing diagrams ls turn off hs turn on csb 90% 90% 10% 10% 90% tlsoff tlstr thstr tlsoff hson thson hs turn off ls turn on csb 90% 90% 10% 10% 90% thsoff tlson tlstf thstf thsoff lson figure 4. detailed driver timing
ncv7718 http://onsemi.com 10 csb sclk 3 5 1 2 4 7 6 8 9 csb so 10 11 12 so sclk si figure 5. detailed spi timing
ncv7718 http://onsemi.com 11 typical performance graphs figure 6. iqtot vs. temperature figure 7. i(vcc) active mode vs. v(vcc) temperature ( c) vcc voltage (v) 150 100 50 0 ? 50 0 0.5 1.5 2.0 3.0 3.5 4.0 5.0 5.5 5.0 4.5 4.0 3.5 3.0 1.40 1.50 1.55 1.60 1.70 figure 8. rdsonls vs. temperature figure 9. rdsonhs vs. temperature ambient temperature ( c) ambient temperature ( c) 150 100 50 0 ? 50 0.5 0.7 0.9 1.3 1.5 1.7 2.1 2.3 150 100 50 0 ? 50 0.5 0.7 0.9 1.1 1.3 1.7 1.9 2.1 figure 10. isdsrc vs. temperature figure 11. isdsnk vs. temperature ambient temperature ( c) ambient temperature ( c) 150 100 50 0 ? 50 iqtot, total sleep mode current ( a) acitve mode vcc current (ma) ls rdson ( ) hs rdson ( ) high side over current (a) 1.0 2.5 4.5 v cc = 5.25 v v cc = 5 v v cc = 3.15 v 1.45 1.65 1.1 1.9 1.5 hs1 hs2 hs3 hs4 hs5 hs6 hs1 hs2 hs3 hs4 ls1 ls2 ls3 ls4 ls5 ls6 150 c ? 40 c 125 c 25 c 15 0 100 50 0 ? 50 0.5 0.7 0.9 1.1 1.3 1.5 1.9 2.1 low side over current (a) 1.7 ls1 ls2 ls3 ls4 ls5 ls6 0.5 0.7 0.9 1.3 1.5 1.7 2.1 1.1 1.9 hs1 hs2 hs3 hs4 hs5 hs6
ncv7718 http://onsemi.com 12 typical performance graphs figure 12. isdsnk vs. temperature ambient temperature ( c) 150 100 50 0 ? 50 0 0.05 0.10 0.15 0.20 0.25 sink leakage current ( a) ls1 ls2 ls3 ls4 ls5 ls6 figure 13. isrclkg13.2 vs. temperature ambient temperature ( c) 150 100 50 0 ? 50 ? 0.2 0 0.2 0.4 0.6 0.8 1.2 ? source leakage current ? ( a) 1.0 hs1 hs2 hs3 hs4 hs5 hs6 figure 14. ibdfwd vs. current current (a) 150 100 50 0 ? 50 0 0.2 0.6 0.8 1.0 body diode forward voltage (v) 0.4 1.2 hsx lsx
ncv7718 http://onsemi.com 13 operating description general overview the ncv7718 is comprised of twelve dmos power drivers (six pmos high side driver and six nmos low side driver) configured as six half bridges that enables three independent full bridge operations. each output drive is characterized for a max 550 ma dc load and has a typical 1.2 a surge capability (at v sx =13.2 v). strict adherence to integrated circuit die temperature is necessary. maximum die temperature is 150 c. this may limit the number of drivers enabled at one time. output drive control and fault reporting is handled via the spi (serial peripheral interface) port. an enable function (en) provides a low quiescent sleep current mode when the device is not being utilized. no data is stored when the device is in sleep mode. an internal pull down resistor is provided on the en input to ensure the device is off if the input signal is lost. de ? asserting the en signal clears all the registers and resets the driver. when the en signal is asserted the ic will proceed with the v cc por cycle and brings the drivers into normal operation. spi communication 16 ? bit full duplex spi communication has been implemented for the communication of this ic for device configurations, driver controls and reading the diagnostic data. in addition to the 16 ? bit diagnostic data, a pseudo bit (pre_15) can also be retrieved from the so register. the part is required to be enabled (en active high) for spi communication. the inputs for the spi are ttl logic compatible and are specified by the vthinh and vthinl thresholds. the active low csb input has a pull up resistor and the remaining spi inputs have pull ? down resistors to bias them to a known state when spi is not active. reference the spi communication frame format diagram in figure 15 for the 16 bit spi implementation. tables 1 and 2 define the programming bits and diagnostic bits shown in figure 15. spi communication frame format figure 15. spi communication frame format csb si so sclk ssr hbsel psf hbcnf6 ? hbcnf1 ovlo tw hben6 ? hben1 uld 0 14 13 15 ocs uld hbst6 ? hbst1 hbcr6 ? hbcr1 tsd communication is implemented as follows and is also illustrated in figure 18: 1. si and sclk are set to low before the csb cycle. 2. csb goes low to allow serial data transfer. 3. si data starting with the most significant bit (msb) is shifted in first. 4. si data is recognized on every falling edge of the clock. 5. simultaneously, so data from the previous frame starting with the msb bit is shifted out on every rising edge of the clock. 6. the input data is compared to a 16 bit counter for the initial 16 bits shifted into si for frame detection error scheme. 7. the sequential input bits are compared to a n x 8 ( n can take on the value of any integer) bit counter for daisy chain operations and are monitored by the frame detection error scheme. 8. csb goes high and the most recent 16 bits clocked into si are transferred to the data register given that there is no frame detection error. otherwise the entire frame is ignored. 9. so is tri ? state when csb is high.
ncv7718 http://onsemi.com 14 table 1. spi input data frame input data bit number bit name bit description bit status 15 srr status reset register when asserted all latched faults are cleared (ocd, uld & tsd) 0 = no reset 1 = reset 14 hbsel (note 4) half bridge selection need to be set to zero 13 uldsc under load detection shutdown control global enable; per half bridge operation 0 = disable 1 = enable 12 hben6 half bridge 6 enable 0 = high z 1 = enabled 11 hben5 half bridge 5 enable 0 = high z 1 = enabled 10 hben4 half bridge 4 enable 0 = high z 1 = enabled 9 hben3 half bridge 3 enable 0 = high z 1 = enabled 8 hben2 half bridge 2 enable 0 = high z 1 = enabled 7 hben1 half bridge 1 enable 0 = high z 1 = enabled 6 hbcnf6 half bridge 6 configuration control 0 = ls6 on & hs6 off 1 = ls6 off & hs6 on 5 hbcnf5 half bridge 5 configuration control 0 = ls5 on & hs5 off 1 = ls5 off & hs5 on 4 hbcnf4 half bridge 4 configuration control 0 = ls4 on & hs4 off 1 = ls4 off & hs4 on 3 hbcnf3 half bridge 3 configuration control 0 = ls3 on & hs3 off 1 = ls3 off & hs3 on 2 hbcnf2 half bridge 2 configuration control 0 = ls2 on & hs2 off 1 = ls2 off & hs2 on 1 hbcnf1 half bridge 1 configuration control 0 = ls1 on & hs1 off 1 = ls1 off & hs1 on 0 ovlo over voltage lock out global effect 0 = disable 1 = enable 4. hbsel enables bridge selection for the ncv7719 and ncv7720 devices. in the ncv7718 if the hbsel is set to ?1? then the entire frame is ignored.
ncv7718 http://onsemi.com 15 table 2. spi output data frame output data bit number bit name bit description bit status pre_15 tsd latched thermal shutdown 0 = no fault 1 = fault 15 ocs over current shutdown global notification 0 = no fault 1 = fault 14 psf power supply failure on vs1 and/or vs2 under voltage and over voltage monitoring 0 = no fault 1 = fault 13 uld under load detection global notification 0 = no fault 1 = fault 12 hbst6 half bridge 6 enable status 0 = high z 1 = enabled 11 hbst5 half bridge 5 enable status 0 = high z 1 = enabled 10 hbst4 half bridge 4 enable status 0 = high z 1 = enabled 9 hbst3 half bridge 3 enable status 0 = high z 1 = enabled 8 hbst2 half bridge 2 enable status 0 = high z 1 = enabled 7 hbst1 half bridge 1 enable status 0 = high z 1 = enabled 6 hbcr6 half bridge 6 configuration reporting 0 = ls6 on & hs6 off 1 = ls6 off & hs6 on 5 hbcr5 half bridge 5 configuration reporting 0 = ls5 on & hs5 off 1 = ls5 off & hs5 on 4 hbcr4 half bridge 4 configuration reporting 0 = ls4 on & hs4 off 1 = ls4 off & hs4 on 3 hbcr3 half bridge 3 configuration reporting 0 = ls3 on & hs3 off 1 = ls3 off & hs3 on 2 hbcr2 half bridge 2 configuration reporting 0 = ls2 on & hs2 off 1 = ls2 off & hs2 on 1 hbcr1 half bridge 1 configuration reporting 0 = ls1 on & hs1 off 1 = ls1 off & hs1 on 0 tw thermal warning global notification 0 = no fault 1 = fault if the half ? bridge enable status denotes a high impedance condition (hbstx = 0), the corresponding half ? bridge configuration reporting (hbcrx) should be ignored. the latched thermal shutdown (tsd) information is available on so after csb goes low until the first rising sclk edge. the following procedures must be met for a true tsd reading: 1. sclk and si are low before the csb cycle. violating these conditions will results in an undetermined spi behavior or/and an incorrect tsd reading. 2. csb transitioning from high to low. 3. csb setup time (tcsbsup) is satisfied and the data is captured before the first sclk rising edge.
ncv7718 http://onsemi.com 16 driver control the ncv7718 has the flexibility of controlling each driver through the 16 bit spi frame (bits 12 ? 1) and the logic combination required for bridge control is defined in figure 16. hbenx hbcnfx outx vs hsx lsx hbenx hbcnfx outx 0 ?x? outx in high impedance state 1 0 hsx off and lsx on 1 1 hsx on and lsx off ?x? = don?t care figure 16. bridge control logic the digital design insures that the high side and low side of the same half bridge will not be active at the same time. thus the device self protects from a current shoot through condition. delays (thsofflson and tlsoffhson) between the high side and low side switching are implemented for same reasons. frame detection to maintain the data integrity, the ncv7718 has 16 bit frame detection. a valid frame for a single csb cycle requires 16 bits to be clocked into si for the initial 16 bits and n x 8 bits thereafter. in an instance of an invalid spi frame the entire frame is ignored, but the previous states of the corresponding outputs are maintained. daisy chain operation daisy chain communications between multiple of 8 ? bit spi compatible ic?s is possible by connection of the serial output pin (so) to the input of the sequential ic (si). the clock phase and clock polarity respect to the data must be the same for all the devices on the chain. figure 17 illustrates the hardware configuration of ncv7718 daisy chained with a n*8 bit (ie n = 2; 16 bit) spi device. the progression of data from the mcu through the sequential devices is also shown. strict adherence to the frame format illustrated in figure 18 is required for the proper serial daisy chain operations.
ncv7718 http://onsemi.com 17 mcu ncv7718 16 bit spi csb sclk mo csb sclk si mi so n*8 bit spi device (ie n=2; 16 bits) csb sclk si so device1 device2 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits command bits for the device 2 previous diagnostic bits from device2 command bits for device 1 previous diagnostic bits from device1 figure 17. serial daisy chain if device 2 is a 16 bit ic, then a total of 32 bits must be generated from the mcu for a complete transport of data in the system. monitoring of all the devices in the serial chain must be employed on a system level architecture. thus, pre ? cautious measure should be taken to avoid situations where not enough frames were sent to the devices, but the frames transmitted did not violate the internal frame detection counters. for these scenarios, invalid data is accepted by ncv7718 and possibly by other devices on the chain depending on their frame detection design. the data shifted in will be transferred to the data registers of the devices on the beginning of the chain and the devices at the end of the chain will get the previous diagnostic data of the preceding devices.
ncv7718 http://onsemi.com 18 figure 18. spi data recognition and frame detection sclk csb si 7 6 1 0 15 word b ? 8 bits word a ? 16 bits 24 bit frame modulo16 counter begins on the first rising sclk edge after csb goes low . si data is recognized on the falling sclk edge . so data is shifted out on the rising sclk edge . tsd so msb msb lsb lsb msb msb 0 lsb lsb 8 7 modulo16 counter ends? 16 bit word length valid . modulo8 counter begins on the next rising sclk edge . modulo8 counter ends? 8 bit word length valid . valid n*8 bit frame. the tsd bit is multiplexed with the spi so data and or?d with the si input (figure 19) to allow for reporting in a serial daisy chain configuration in devices with the same spi protocol. a tsd error bit as a ?1? automatically propagates through the serial daisy chain circuitry from the so output of one device to the si input of the next. this is shown in figures 20 and 21; first as the daisy chained devices connected with no thermal shutdown latched fault (figure 20) and subsequently with a tsd fault in device 1 propagating through to device 2 (figure 21). tsd spi si so s so si tsd so ncv7718 si tsd so ncv7718 ?0? ?0? ?0? ?0? ?0? device #1 device #2 figure 19. tsd spi link figure 20. daisy chain no tsd fault si tsd so ncv7718 si tsd so ncv7718 ?0? ?1? ?1? ?0? ?1? device #1 device #2 figure 21. daisy chain tsd error propagation
ncv7718 http://onsemi.com 19 device protection, diagnostics and fault reporting power up/down control each analog power pin (vs1 or vs2) powers their respective output drivers. after a device has p owered up and the output drivers are allowed to turn on, the output drivers will not turn off until the voltage on the supply pins is reduced below the initial under voltage threshold, exceeds the over voltage threshold or if shut down by either a spi command or a fault condition. internal power ? up circuitry on the logic supply pin supports a smooth turn on transition. vcc power up resets the internal logic such that all output drivers will be off as power is applied. all the internal counters, si and so along with all the digital registers will be cleared on vcc por. exceeding the under voltage lockout threshold on vcc allows information to be input through the spi port for turn on control. logic information remains intact over the entire vs1 and vs2 voltage range. under voltage shutdown an under voltage lockout circuit prevents the output drivers from turning on unintentionally. this control is provided by monitoring the voltages on the vs1, vs2 and vcc pins. a built ? in hysteresis on the under voltage threshold is included to prevent an unknown region on the power pins; vcc, vs1 and vs2. when the vcc goes below the threshold, all outputs are turned off and the input and output registers are cleared. an under voltage condition on the vsx pins will result in shutting off all the drivers and the status bit 14 (psf) will be set. the spi port remains active during a vsx under ? voltage if proper vcc voltage is supplied. also all driver states will be maintained in the logic circuitry with the valid vcc voltage. once the input voltage vsx is above the under voltage threshold level the drivers will return to programmed operation and the psf output register bit is cleared. under ? voltage timing diagram is provided in figure 22. figure 22. under ? voltage timing diagram outx ls ? outx ls ? x no fault outx ls psf all z outx ls no fault 0x00 all z vsx vcc ? outx hs outx hs vsuv vccuv no fault psf no fault 0x00 outx vs no fault outx hs no fault t outx gnd outx gnd si status output state so z
ncv7718 http://onsemi.com 20 over voltage shutdown over voltage shutdown circuitry monitors the voltage on the vs1 and vs2 pins, which permits a 40 v maximum. when the over ? voltage threshold level has been breached on the vs1or vs2 supply input, the output bit 14 (psf) will be set. additionally, if the input bit 0 (ovlo) is asserted, all outputs will turn off. during an over voltage lockout condition the turn on/off status is maintained in the logic circuitry. when proper input voltage levels are re ? established, the programmed outputs will turn back on. over ? voltage shutdown can be disabled by using the spi input bit 0 (ovlo = 0) to run through a load dump situation. it is highly recommended to operate the part with ovlo bit asserted to ensure that the drivers remain off during a load dump scenario. the table below describes the driver status when enabling/disabling the over voltage lock out feature during normal and overvoltage situations. table 3. over ? voltage lock out (ovlo) ovlo input bit vsx ovlo condition output data bit 14 power supply fail (psf) status outx status 0 0 ?0? not in overvoltage outputs unchanged 0 1 ?1? (clears when vsx within operating range) in overvoltage outputs unchanged 1 0 ?0? not in overvoltage outputs unchanged 1 1 ?1? (clears when vsx within operating range) all outputs off (remain off until vsx is out of ovlo) over ? voltage timing diagram is provided in figure 23. figure 23. over ? voltage timing diagram ? ? outx on psf all z vsx vsov psf no fault no fault t si status output state so outx on ovlo=0 x outx on no fault no fault outx on outx on ovlo=1 no fault vsov psf psf outx on outx on no fault outx off no fault outx z
ncv7718 http://onsemi.com 21 over current detection and shutdown the ncv7718 of fers over current shutdown protection on the outx pins by monitoring the current on the high side and low side drivers. if the over current threshold is breached, the corresponding output is latched off (hs and ls driver is latched off) after the specified shutdown time, tdoc. upon over current shutdown, the serial output bit ocs will be set to denote a high power dissipation state. devices can be turned back on via the spi port once the ocs bit is cleared by setting the srr to ?1? on the next spi command. the event triggering the over current shutdown condition must be resolved prior to clearing the ocs bit to avoid repetitive stress on the drivers. failure to do so may result in non reversible fatal damage. note: high currents could cause a high rise in die temperature. devices will turn off if the die temperature exceeds the thermal shutdown temperature. figure 24. over ? current timing diagram outx on ocs isdsxx t si status output state so outx on srr=0 outx on no fault outx on srr=1 outx on outx z output current outx on no fault no fault tdoc ocs outx z tdoc outx on no fault no fault outx on ocs ocs ocs under load detection the under ? load detection is accomplished by monitoring the current from the low side drivers and one global output bit is used for under load fault reporting. a minimum load current (iuldls ? this is the maximum open circuit detection threshold) is required when the drivers are turned on to avoid an under ? load condition. if the under ? load detection threshold has been breached longer than the specified under ? load timer (tduld), the uld output bit is set to ?1?. furthermore, if the under ? load detection shutdown control (uldsc bit # 13) input bit is set then the of fending half ? bridge output will be turned off (hs and ls on the driver will be latched off). there is only one global under load timer for all the drivers. if the tduld timer is already activated due to one under load, any subsequent under load delays will be the remainder of the tduld timer. table 4. under ? load driver status uldsc input bit 13 outx uld condition output data bit under load detect status outx status 0 0 ?0? unchanged 0 1 ?1? (need srr to reset) unchanged 1 0 ?0? unchanged 1 1 ?1? (need srr to reset) outx latches off (need srr to reset)
ncv7718 http://onsemi.com 22 under ? load timing diagram is provided in figure 25. figure 25. under ? load timing diagram si status output state so output current t lsx on uldsc=0 lsx on no fault lsx on srr=1 no fault no fault uld outx on no fault uld uld lsx on uldsc=1 uld lsx on srr=1 lsx on uld outx gnd iuldls tduld tduld outx z outx gnd no fault no fault tduld thermal warning and thermal shutdown the ncv7718 provides individual thermal sensors for each half ? bridge. moreover, the sensor reports over temperature warning level and an over temperature shutdown level. the tw status bit (output bit 0) will be set if the temperature exceeds the over temperature warning level, but the drivers will remain active. once the ic temperature fall below the thermal warning threshold the tw flag is automatically clearly. if any of the individual thermal sensors detects a thermal shutdown level then the drivers on the of fending half bridge are latched off. the tsd (pre_15) bit is set to capture a thermal shutdown event. a valid spi command with srr and temperature below the tsd threshold are required to clear the latched fault. since thermal warning precedes an over temperature shutdown, software polling of this bit will allow load control and possible prevention of over temperature shutdown conditions. figure 26. thermal warning and shutdown timing diagram outx on t si status output state so outx on no fault tsd twr t j tw no fault tw outx on no fault no fault outx on tw outx on tw outx z twhy tsdhy outx on srr=1 tsd tw tsd tw tw outx on srr=1 tw outx on tw
ncv7718 http://onsemi.com 23 thermal performance figure 27. ja vs. cu area copper heat spreader area (mm 2 ) 800 600 500 400 300 200 100 0 60 70 90 100 110 130 150 160 ja ( c/w) 700 900 80 120 140 1.0 oz 2.0 oz figure 28. r(t) vs. duty cycle on 600 mm 2 spreader area over 2 oz copper 0.000001 0.0001 0.01 1 100 0.01 0.1 1 10 100 1000 pulse time (sec) r(t) ( c/w) single pulse 1% 2% 5% 10% 25% duty = 50%
ncv7718 http://onsemi.com 24 table 5. ssop24 thermal rc network models foster thermal network cauer thermal network 200 mm 2 900 mm 2 200 mm 2 900 mm 2 r c r c r c r c c/w w ? sec/c c/w w ? sec/c c/w w ? sec/c c/w w ? sec/c 2.00e ? 02 5.00e ? 05 2.00e ? 02 5.00e ? 05 1.49e ? 01 1.74e ? 05 1.49e ? 01 1.74e ? 05 2.00e ? 01 5.00e ? 05 2.00e ? 01 5.00e ? 05 5.67e ? 01 1.27e ? 05 5.67e ? 01 1.27e ? 05 1.70e+00 5.88e ? 05 1.70e+00 5.88e ? 05 1.32e+00 4.19e ? 05 1.32e+00 4.19e ? 05 1.20e+00 2.92e ? 03 1.20e+00 2.92e ? 03 2.55e+00 1.94e ? 03 2.55e+00 1.94e ? 03 2.70e+00 8.52e ? 03 2.70e+00 8.52e ? 03 4.90e+00 5.08e ? 03 4.88e+00 5.09e ? 03 3.50e+00 3.43e ? 02 3.50e+00 3.43e ? 02 1.10e+01 1.44e ? 02 1.08e+01 1.45e ? 02 7.40e+00 5.95e ? 02 7.40e+00 5.95e ? 02 1.58e+01 2.84e ? 02 1.53e+01 2.91e ? 02 2.32e+01 9.05e ? 02 2.32e+01 9.05e ? 02 2.12e+01 6.53e ? 02 1.97e+01 6.90e ? 02 2.71e+01 3.69e ? 01 2.71e+01 3.69e ? 01 2.59e+01 3.66e ? 01 1.93e+01 4.45e ? 01 4.59e+01 1.53e+00 2.24e+01 3.13e+00 2.95e+01 1.78e+00 1.48e+01 4.05e+00 the cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. the foster networks, though when sorted by times constant (as above) bear a rough correlation with the cauer networks, are really only convenient mathematical models. both foster and cauer networks can be easily implemented using circuit simulating tools, whereas foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: r(t) n i 1 r i 1 e ? t i figure 29. grounded capacitor network (?cauer? ladder?) figure 30. non ? grounded capacitor network (?foster? ladder?)
ncv7718 http://onsemi.com 25 fault handling at an event of a driver latched off fault, the offending half ? bridge driver is disabled and the half ? bridge configuration is defaulted to zero (hbenx =0, hbcnfx = 0). the user is required to clear the output register fault and to resend the proper spi frame to turn on the drivers. a driver that is locked out during a fault conditions auto recovers to the previous programmed state when the fault is resolved. a latched fault flag on the serial output doesn?t always translate an output latched off fault. the summary of all fault conditions, the driver status and the clear requirements are provided in table 6. table 6. fault summary fault fault memory serial output bit driver condition during fault driver condition after parameters within specified limits output register clear requirement under load (uldsc = 0) latched outputs unchanged. allowed to turn/ remain on allowed to turn/remain on valid spi frame with srr set to 1 under load (uldsc = 1) latched (note 5) offending half ? bridge is latched off (ls and hs) offending half ? bridge is latched off (ls and hs) valid spi frame with srr set to 1 over current latched (note 5) offending output is latched off (ls and hs) offending output is latched off (ls and hs) valid spi frame with srr set to 1 thermal warning non ? latched outputs unchanged. allowed to turn/ remain on provided that device is not in thermal shutdown allowed to turn/remain on temp below (thermal warning temp ? hysteresis) thermal shutdown latched (note 5) offending half ? bridge drivers are latched off (ls and hs) offending half ? bridge is latched off (ls and hs) valid spi frame with srr set to 1. temperature blow (thermal shutdown ? hysteresis) vs power supply fail (over ? voltage: ovlo = 0) non ? latched outputs unchanged. allowed to turn/ remain on allowed to turn/remain on vs below (over voltage threshold ? hysteresis) vs power supply fail (over ? voltage: ovlo = 1) non ? latched all drivers are locked out. outx high z previous half ? bridge status and driver configuration is maintained. allowed to turn/remain on auto recovers if the vs voltage is below overvoltage threshold vs power supply fail (under voltage) non ? latched all drivers are locked out. outx high z previous half ? bridge status and driver configuration is maintained. allowed to turn/remain on auto recovers if the vs voltage is above the under voltage threshold 5. latched conditions are cleared via the spi srr input bit = 1, by cycling the en pin or with a power ? on reset of v cc .
ncv7718 http://onsemi.com 26 application diagram the application drawing below demonstrates the drive capability of the ncv7718. the vs1 and vs2 pins must be tied together to avoid any potential difference in the supply voltage. ncv7718 hex half bridge gnd gnd gnd en vcc si so sclk csb vs1 vs2 out1 out2 m1 out3 out4 m2 out5 out6 m3 uc en mosi miso sclk csb ncv8518b delay wdi vout en gnd vcc vin 20k 120k reset io reset mra4003t3 0.1uf 13.2v 1.0uf gnd m5 m4 figure 31. application drawing ordering information device package shipping ? NCV7718DPR2G ssop24 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv7718 http://onsemi.com 27 package dimensions case 565al ? 01 issue o dim min max millimeters a 1.75 a1 0.10 0.25 l 0.40 1.27 e 0.65 bsc c 0.19 0.25 h 0.22 0.50 b 0.20 0.30 l2 0.25 bsc m 0 8 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. 4. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension e1 does not inlcude inter- lead flash or protrusion. interlead flash or protrusion shall not ex- ceed 0.15 per side. d and e1 are de- termined at datum h. 5. datums a and b are determined at datum h. pin 1 reference d e1 0.10 seating plane 24x b e e detail a 1.35 soldering footprint* l l2 gauge detail a e1 3.90 bsc plane seating plane c c h end view a-b m 0.25 d c top view side view d 0.20 c 112 24 a b d 2x 12 tips a1 a2 c c 24x d 8.65 bsc e 6.00 bsc 24x 1.12 24x 0.42 0.65 dimensions: millimeters pitch 6.40 1 2x a h x 45 12 24 13 m 13 d 0.25 c d 0.20 c 2x 0.10 c recommended a2 1.50 1.25 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncv7718/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of NCV7718DPR2G

	To Download NCV7718DPR2G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .